On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
Explain how an out-of-order processor works? How do you implement register renaming? Difference between an architectural and physical register file
Q: Register renaming. How it works
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
Compare and contrast write-through and write-back caches.
Calculate the number of tag bits for an 8-way set associative cache with 32-bit virtual addresses that is 16kB.
How to write an assertion in SystemVerilog
What is a hardstuck bug you have encountered during a project?
How do you verify this logic block?(a black box with some input and outputs and the timing diagram is given
Some verification related questions were asked?
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