Clock domain crossings and reset domain crossings
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
What is your experience with random constrained stimulus?
about DV methodologies, DV techniques, protocols
digital, verilog, system verilog
show how code coverage and function coverage works. explain with code
APB and AXI protocol explation with all signals.
Tell any 5 commands and how to validate floorplan
questions on digital electronics and verilog
CMOS, jilter, state machine, and, xor, nand gates etc... half hour paper
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