pipeline, fifo in registers/ram, hold/setup and how to correct violations, my undergraduate projects, Circuit with different clock frequencies, circuit with single frequency but clock skew and more.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
electronics the technical questions like find the output of flip-flops find the output at a specific clock cycle combinations of flip flops and mux simplifications of gates transmission gate problem basic electronics like temperature were given flipflops and interview time played a dominant role in the first round
From basics to complex fundamentals
Design basic logic gates (AND, XOR) using a 2to1 mux. Write a module which will take clk as an input and output a clk divided by 3. Important to note that generated clock needs to be an output of the Flop.
Visually Identify between combinational and squential elements
What are your weekness and how can you surpass them in work environment?
RTL coding related questions such as writing a simple FSM.
How can I estimate a new IP complexity and area without having any specific details yet?
design a trafffic light controller
Qhat is your strength? An example of the time that you take initiative? What is your weakness?
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