Why is scrambling, encoding, and equalization used in PCI Express?
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
The interviewer drew two flip flops, told me the frequency of clock and input signal, and let me draw output waveform.
After you design the hardware in Q1, try to design another hardware to show the index of the bits at the same time.
Using only NAND gate to design some logic
Multiclock domain synchronization , dff vs latch
Create a NAND gate using only 2:1 muxs.
Where do you see yourself in 5 years
what is the blocking and non-blocking statement in Verilog?
Will you be able to easily commute to the location?
1) FIFO RTL design 2) how to optimize power 3) steps to take ECO
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