1. Difference between SystemVerilog and Verilog. 2. Difference between nonblocking and blocking. 3. Difference between asynchronous and synchronous. 4. How can you observe and solve the problem if there is a timing violation (related to setup time and hold time)
Describe the process for design of a new architecture and the refinement process
Assume that a certain gate in a logic circuit is always stuck at 1. What test inputs would you need to determine that the logic gate is defective.
What is the CMOS
what is clock uncertainty what is skew
Verilog description of logic. Digital logic questions
Types of coverage?
Create a NAND gate using only 2:1 muxs.
Using only NAND gate to design some logic
Multiclock domain synchronization , dff vs latch
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