Computer Architecture, FIFO depth calculation, how to design Power, Performance, or Area-efficient RTLs, also some questions regarding pipeline hazards.
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
Describe how you solved a problem on a project
Explain ASIC Design Flow
Using 3 registers and two two-bit full adders, how to count to 9 given that one clock cycle is only enough the delay of a full adder.
Number of bits representation for a given math function
Setup time, hold time?
Write the equation for set-up time for the circuit described. Give the hold equation for the same
Round 2 1- RTL coding 2- C, C++ pointer questions 3- how to do VHDL coding 4- FSM Sequence detector 5- How will you verify the FSM code 6- Design Using Shift Registers 7- How will you code this
Design a state machine for sequence detection.
What is Setup and hold time
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