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1,151 analyste soc interview questions shared by candidates

Basic Verilog questions, FSM, Synchronizers, Clock Domain Crossing, Sequence detectors, Clock divider circuits, FIFO, Async FIFO, Circuit to detect the number of 1's using adders and then using only combinational logic, Transpose a Matrix using C. I was asked to code on almost all of the topics mentioned above.
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Soc Design Engineer

Interviewed at Intel Corporation

3.9★
Nov 8, 2017

Basic Verilog questions, FSM, Synchronizers, Clock Domain Crossing, Sequence detectors, Clock divider circuits, FIFO, Async FIFO, Circuit to detect the number of 1's using adders and then using only combinational logic, Transpose a Matrix using C. I was asked to code on almost all of the topics mentioned above.

1. Few questions on writing constraints for certain scenarios. 2. FSM for number divisible by 3 3. UVM subscriber, sequences, TLM ports and FIFO. 4. write code for random number generation for given distribution and ranges. 5. byte addressing in an integer memory system. 6. constrain for non-overlapping segment-addresses generation. 7. Explain any testbench architecture you have worked on. 8. Lots of simple questions to test SystemVerilog and OOP concepts.
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SoC Verification Engineer

Interviewed at Apple

4.1★
Mar 23, 2017

1. Few questions on writing constraints for certain scenarios. 2. FSM for number divisible by 3 3. UVM subscriber, sequences, TLM ports and FIFO. 4. write code for random number generation for given distribution and ranges. 5. byte addressing in an integer memory system. 6. constrain for non-overlapping segment-addresses generation. 7. Explain any testbench architecture you have worked on. 8. Lots of simple questions to test SystemVerilog and OOP concepts.

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