Qualcomm RFIC Design Engineer interview questions

Phone interview with one senior engineer and the hiring manager: Senior engineer asked me the following questions: 1. How does the drain current of NMOS transistor vary with temperature change? 2. How does the gain of CS-Amplifer change with the temperature variation? 3. Basic design procedure of power amplifer? 4. Phase noise definition. 5. What cause phase noise of oscillator and PLL? Hiring manager: 1. Cutoff frequency definition, how to calculate it of CMOS transistor, how to increase and decrease it? 2. Relationship between transconductance and width of transistor/ 3. Input impedance value of CS-Amplifer with source degenerated resistor, inductor or capacitor? 4. Operational Transconductance Amplifer: How does the gain change with drain current change? Some questions on my resume.