Intel Corporation Component Design Engineer interview questions

Received 1 technical phone screen with questions derived from my resume with a few higher level what-if questions. The interviewer was on time with our agreed upon time for the phone conversation. The next step took a little longer because of the July 4th holiday weekend, but was scheduled about 3 weeks after the initial screen. The onsite interview consisted of 3 1hr 1:1s very technical in nature designed to find my breaking point. An off-site lunch with the hiring manager was nice and casual. Compensation expectations were discussed on the ride back to campus. 3 more 1hr 1:1s were scheduled with a different design group and were equally as challenging. I was impressed with the caliber of people that interviewed me and felt like I did very well answering the questions.

Phone interview lasted for 1 hour. Questions were as follows: derive equation from FSM, K-maps, equation reduction using De-morgans law,pipelining and hazards, inverter working, how Vth varied with temp, SRAM working. 2 weeks later was called for onsite interview. Consisted of 4 rounds. 1st round: questions related to system verilog, projects, design FSM from waveforms and conditions given. C code for converting binary to octal. 2nd round: Given a black box and some conditions and asked to design a digital system. Design FF's. Given verilog code and asked to design gate level diagram. 3rd round: Questions related to computer architecture. Asked project related questions.Cache write policies, write back, write through, PCI,PCI-E, arbitration, how to get faster circuits, latest INTEL chipset architecture. Remember all the questions were indirect.Logical questions. 4th round: Timing analysis. Slew, fanout, design flow, setup and hold circuit analysis. Circuit analysis. All questions were logical,none direct. Hope this helps!! All the interviewer's were friendly and co-operative. It was basically like a discussion rather than question and answer session.