HCLTech Design Verification Engineer interview questions

Medium process, 3 rounds were there. Each of one hour. Asked about projects, regarding protocols, regarding Verilog, regarding system verilog, regarding UVM. Past experience with the previous organization. Interview process was good and all the process happen in one day.

Definitely went on well and was a great interview. The interviewer was polite and made me feel comfortable. The interview was about 1 hour to 1 hour 15 minutes. Overall experience was good.