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Description
As a DFT engineer, you will lead the complete DFT solution for a chip project, with responsibilities spanning all aspects of semiconductor development.","responsibilities":"You will create DFT specifications, create verification plans, and define the SoC test interface.
You will develop and implement the DFT architecture and own its integration into large SoC blocks - including IP integration, system and control bus connectivity, and the integration of memories and hard macros.
You will implement testbenches, generate directed and constrained-random tests, debug failures, run gate-level simulations, and close coverage.
You will also generate structural test vectors, run synthesis and timing closure and work closely with Chip Architecture, DV, Physical Design, and Power teams to achieve first-tapeout success.
Additional responsibilities include supporting STA, physical, power, and logical analysis for DFT modes, partnering with Test Engineers to bring up test vectors on silicon.

Preferred Qualifications
Exposure to industry-standard DFT concepts such as ATPG, JTAG, or MBIST.
Knowledge of general logic design principles.
Exposure to design verification methodologies, coverage analysis, and assertions.
Good problem-solving and communication skills.
Experience in large SoC design or verification - a plus.

Minimum Qualifications
B.Sc./M.Sc. in Electrical Engineering, Computer Science, or a related field.
Knowledge of Verilog and/or VHDL, and familiarity with simulators and waveform debugging tools.
Exposure to a scripting language such as Python, TCL, or Perl, including familiarity with leveraging generative AI tools to support scripting and engineering workflows.
Ability to fluently speak and write in English.