Change the world. Love your job.

Job duties of Layout Engineering Intern will include:

• Block level IC layout, top level integration, floor planning, and area estimation
• Power transistor and package lead frame design for discrete and module devices
• Die and package-board parasitic extraction
• Physical verification and post-layout analysis (DRC, LVS, EM, ESD)
• Use advanced tools to automate basic block level layout tasks, floor planning, and area estimations.

• Collaborating with analog/Digital design, and other cross functional teams such as product engineers, program managers, systems etc...
• Participating in layout design reviews
• Design flow automation/verification function development

• Qualified candidates are in their final years of their ongoing studies (master or bachelor) within Electrical Engineering or equivalent
• Please add your latest transcript of grades to your application

• Good understanding of analog electronics theory and device physics.
• Experience of Cadence Virtuoso or equivalent IC layout design tools
• Ability to work in teams and collaborate effectively with people in different functions
• Ability to take the initiative and drive for results
• Strong time management skills that enable on-time project delivery
• Strong analog problem solving skills, IC Layout design experience and knowledge of switching DCDC regulators is a plus
• Unix and Cadence database management skills
• Strong verbal and written communication skills in English, German is a plus
• Shell or other programming language is a plus

Our Offer for you:

• Benefit from an attractive compensation
• Join an international work environment where your ideas count and where you can thrive in a diverse culture
• Explore a world of opportunities for your personal and professional development