2nd phone interview: 1 unit with 9ns delay vs 3 units with delays 2ns, 4ns, 3ns. Which has better throughput and how much?
Verification Manager Interview Questions
3,713 verification manager interview questions shared by candidates
1) Swap in Verilog 2) Print 2D matrix spirally starting from centre 3) randomize the size of a 2D matrix/multi dimentional array 4) Fork-join and how to disable fork 5) Assertions 6) Reverse a string 7) How to verify a vending machine 8) Application of UVM Barrier class, 9) Divide by 5 state machine and extract a mathematical equation to generate the next state , 10) Write a system verilog test to verify if all the clocks on the SOC have been switched off after writing 'b1 to a register , 11) Why do we need UVM agents , 12) How is UVM Scoreboard implemented, 13) Constraint address to word accessible , atleast 2 ways to do it , 14) Test Plan and functional Coverage
What role you want to be in 5 years.
Write UVM Monitor for the defined case.
They asked me about my work experience and the day to day activities in my present company.
why you choose this role at BNP
What was the most difficult thing you had to deal with a customer and how did you handle it.
They gave me few written programmes and asked me to explain the programme flow
Can u join us aaand give me money. We will train you and then give u job.
SV UVM based question, purpose of uvm_config_db, uvm testbench architecture
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