The first interview asked basic technical questions about logic design, STA and FSM etc. The second one was RTL coding for synchronous FIFO with depth=5
Asic Engineer Interview Questions
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Design a MUX using only NOT, AND and OR gates
What is clock domain crossing?
They asked me one question related to my project in verilog, that is how to make a digital clock using verilog in a FPGA board. They then asked me about counters and all. They also asked some questions related to CMOS, one question they asked from the OT and at last they asked me one brain puzzle.
1. linked list 2. setup and hold problems 3. fsm for a particular sequence 4. stuck @ fault 5. circuit design for given waveform 6. verilog coding 7. project related questions 8. edge detector circuit 9. finding number of trailing zeroes in a factorial 10. reverse of a string 11. 3 black cap and 2 white cap puzzle 12. system verilog related questions 13. diff b/w blocking and non-blocking statements 14. basics should be strong
Questions on the resume. SV constructs, FIFO depth, STA questions
All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Sequence detector with FSM Synchronization Cache
Describe a time when you need to gather information from different sources to troubleshoot an issue.
Write verilog code for D ff.
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