1. Verilog question: given 1 bit data, clock and 1 output. Every clock rise- the data is sampled. You need to turn on the output bit every time there is a sequence of 4 bits -1101.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
What would be the effect of adding ESD protection to an output driver.
FIFO Design was the toughest of all the questions they asked me
UPF file in low power design
Describe a scenario when you had to work in a group, or manage project, or resolve conflict, etc
How to do CDC, why gray codes
What is polymorphism?
1. Ways to check if there is any overlapping between cells in a multi-million cell design. (Perl related) 2. How to check the correctness of the scan chains in the design?
Draw a inverter in logic form and in CMOS configuration. And explain the physics behind it.
Create a clock divider
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